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1 ? fn6684.0 isl97648 integrated tft lcd supply and logic driver the isl97648 represents a high power, integrated lcd supply ic which is targeted at notebook, monitor and tv lcd displays. the isl97648 integrates a level shift with charge sharing function, boost converter for a vdd generation of high power with hvs and temperature sensor, 4 high power v com amplifiers, and i 2 c lcd vcom digital calibrator. the isl97648 integrates a high -performance boost converter with 2.7a fet for generating a vdd supply up to 18v. the isl97648 has a high voltage tft-lcd logic driver with +40v and -25v output swing capability. it is capable of delivering 100ma output peak current into 5nf of capacitive load. to simplify external ci rcuitry, the isl97648 integrates additional logic circuits. the integrated hvs circuit is used to provide high voltage stress testing of the lcd panel for production purpose. an on-board temperature sensor is also provided for system thermal management control. the 4 integrated amplifiers fe ature high slew-rate and high output current capability. t hey are permanently enabled when a vdd is present. the vcom voltage of an lcd panel needs to be adjusted to remove flicker. this part provid es a digital interface to control the sink-current output that at taches to an external voltage divider. the increase in output sink current lowers the voltage on the external divider, which is applied to an external vcom buffer amplifier. the desired vcom setting is loaded from an external source via a standard 2 wire i 2 c serial interface. at power-up the part automatically comes up at last programmed setting in an on-board 7-bit eeprom. the isl97648 is packaged in a 56 ld, 8mmx8mm tqfn package and is specified for op eration over the -40c to +85c temperature range. features ? 2.6v to 5.5v input supply ? integrated 2.7a boost converter ? 1.4mhz switching frequency ? level shifter - up to 332khz input logic frequency - +40v to -25v output swing capability - 100ma output peak current - ttl-compatible logic input ? four high speed v com amplifiers ? 5c accuracy thermal sensor over the -40c to +150c temperature range. ?i 2 c calibrator - 128-step adjustable sink current output - output adjustment set pin ? 56 ld 8mmx8mm tqfn package ? pb-free (rohs compliant) applications ? lcd-notebook, monitor and tv ? industrial/medical lcd displays ordering information part number (note) part marking package (pb-free) pkg. dwg. # ISL97648IRTZ 97648irtz 56 ld 8x8 tqfn l56.8x8d ISL97648IRTZ-t* 97648irtz 56 ld 8x8 tqfn l56.8x8d ISL97648IRTZ-tk* 97648irtz 56 ld 8x8 tqfn l56.8x8d *please refer to tb347 for details on reel specifications. note: these intersil pb-free pl astic packaged products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate plus anneal - e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. data sheet april 14, 2008 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 fn6684.0 april 14, 2008 pinout isl97648 (56 ld tqfn) top view ckv1 von sgnd voff 56 55 54 53 52 51 50 49 48 47 46 45 temp hvs rhvs fb comp agnd en vin 44 43 pgnd2 pgnd1 sw2 sw1 test avdd cgnd vcom4 in4- in4+ vcom3 in3- in3+ vcom2 in2- in2+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 42 41 40 39 38 37 36 35 34 33 32 31 30 29 ckvcs1 ckvbcs1 ckvb1 stvp1 stvp2 ckvb2 ckvbcs2 ckvcs2 ckv2 stv1 stv2 cpv1 cpv2 oe 15 16 17 18 19 20 21 22 23 24 25 26 27 28 oecon lgnd dish vdd wpn scl_s scl sda wpp rset out in1+ in1- vcom1 thermal pad connected to gnd isl97648
3 fn6684.0 april 14, 2008 absolute maxi mum ratings (t a = +25c) thermal information all other pins except the following . . . . . . . . . . . . . . -0.3v to +6.5v vin to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . -0.3v to 6.5v vdd to pgnd, agnd, and lgnd. . . . . . . . . . . . . . . . . . . . . . . 6.5v sw to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . . -0.3v to 22v en, fb, comp, temp, hvs, rhvs to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . . . -0.3v to 6.5v in1+, in1-, and vcom1 to pgnd, agnd, and lgnd . -0.3v to 20v in2+, in2-, and vcom2 to pgnd, agnd, and lgnd . -0.3v to 20v in3+, in3-, and vcom3 to pgnd, agnd, and lgnd . -0.3v to 20v in4+, in4-, and vcom4 to pgnd, agnd, and lgnd . -0.3v to 20v avdd to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . -0.3v to 22v dish to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . -3.6v to 5.5v oecon to pgnd, agnd, and lgnd . . . . . . . . . . . . . -0.3v to 5.5v v on to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . . . . . . . . .44v v off to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . . . . . . . -28v v ckv1, v ckv2, v ckvb1, v ckvb2, v ckvcs1, v ckvcs2, v ckvbcs1, v ckvbcs2, stvp1,stvp2 to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . . . . . . -28v to 44v sda, scl, scls-s, w pn , w pp to pgnd, agnd, and lgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 4v out to pgnd, agnd, and lgnd. . . . . . . . . . . . . . . . . . . . . . . .20v voltage between pgnd, agnd, and lgnd . . . . . . . . . . . . . +-0.5v thermal resistance (typical) ja (c/w) jc (c/w) tqfn package (notes 1, 2). . . . . . . . . 48.33 12.07 functional junction temperature (t junction ). . . -40c to +125c storage temperature (t storage ) . . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions operating temperature (t a ) . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured with the component mounted on a low effective therma l conductivity test board in free air. see tech brief tb379 fo r details. 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications vdd = v in = 3.3v, a vdd = 12v, v on = 20v, v off = -14v, t a from -40c to +85c, fcpv1 and fcpv2 = 105khz, unless otherwise specified. unless ot herwise specified, parts are 100% tested at +25c. temperature limits established by characterization and are not production tested. parameter description conditions min typ max unit v dd v dd supply range -- operating 2.25 3.6 v v dd supply range -- eeprom programming 2.6 3.6 v v in analog supply voltage 2.2 3.3 5.5 v avdd avdd output voltage 5 18 v v on positive supply voltage 25 40 v v off negative supply voltage -25 -15 v i in_q input quiescent current not switching (ovp active) 3 ma pin en to ground 1 a boost r (ds)on switch on-resistance v in = 2.7v, i sw = 1a 200 450 m v fb / v in feedback voltage line regulation 2.2v < v in < 5.5v, i out = 200ma, v avdd =8v, l = 6.8h, c out = 10f 2.9 5 mv/v v avdd / i out load regulation 50ma < i out < 0.5a, v in = 3.3v, v avdd =7.8v, l = 6.8h 90 mv/a v fb boost feedback voltage closed loop: v avdd = 8v, l = 6.8h, i out = 200ma, t a = +25c 1.205 1.230 1.255 v i b fb pin bias current 0.1 a i rhvs rhvs pin leakage current hvs pin to ground 100 na res hvs hvs pin resistor hvs pin to ground 105 130 155 v ih hvs input voltage high v in = 2.2v 1.5 v v il hvs input voltage low 0.44 v isl97648
4 fn6684.0 april 14, 2008 t ss soft-start time 10 ms d max max duty cycle 80 85 % d min min duty cycle 15 20 % f osc oscillator switching frequency v avdd = 8v, i out = 200ma, l = 6.8h, d = zhc750, c out = 30f 1.1 1.38 1.5 mhz i l switch leakage current 10 a t sh thermal shutdown threshold activation threshold 150 c de-activation threshold 130 c th en enable threshold output high 0.7 1.1 v i en enable pin current 0.1 a i ocp overcurrent protection in the power mos l = 6.8h 2.2 2.7 3.2 a ovp overvoltage protection on threshold 18.5 21.5 v ovp_hys overvoltage protection hysteresis 2 v uvlo undervoltage protection on threshold 2.0 2.1 2.2 v uvlo_hys uvlo hysteresis 100 mv vcom amplifiers r load = 10k , c load = 10pf, unless otherwise stated i samp supply current 4 op amps combined 8 18 ma v samp supply voltage 5 8 18.5 v cmrr common mode rejection ratio 50 70 db psrr power supply rejection ratio 70 85 db voh output voltage swing high i out (source) = 5ma a vdd - 0.05 v i out (source) = 50ma a vdd - 0.5 v vol output voltage swing low i out (sink) = 5ma 0.05 v i out (sink) = 50ma 0.5 v v offset input offset voltage (v in+ ) - (v in- ) = v offset -15 15 mv bw bandwidth -3db gain point 30 mhz i b inx+, inx-, (x = 1, 2, 3, 4) -1000 100 1000 na sr slew rate 40 v/s i sc output short circuit current 150 250 ma temperature sensor, t a = +25c i temp drive current for +1c additional error 70 a v temp offset output voltage at t j = +100c 1.600 v t accuracy temperature accuracy +50c < t j < +150c 5 c t ratio temperature coefficient 9.5 mv/c level shift, t a = +25c , 4.7nf in series with 50 loadings on ckv1, ckv2, ckvb1, ckvb2 v on positive supply voltage 25 40 v v off negative supply voltage -25 -15 v f cpv operating frequency on cpv1, cpv2 inputs 105 166 khz f oe operating frequency on oe input 210 332 khz electrical specifications vdd = v in = 3.3v, a vdd = 12v, v on = 20v, v off = -14v, t a from -40c to +85c, fcpv1 and fcpv2 = 105khz, unless otherwise specified. unless ot herwise specified, parts are 100% tested at +25c. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit isl97648
5 fn6684.0 april 14, 2008 i dd vdd average supply current (v avdd < 4v) cpv1 = cpv2 = 0, stv = 0, oe = 105khz 500 1000 a i cpv1 cpv1 input current cpv1 = 1 -0.1 0.1 a cpv1 = 0 -0.1 0.1 a i cpv2 cpv2 input current cpv2 = 1 -0.1 0.1 a cpv2 = 0 -0.1 0.1 a i stv1 stv1 input current stv1 = 1 -0.1 0.1 a stv1 = 0 -0.1 0.1 a i stv2 stv2 input current stv2 = 1 -0.1 0.1 a stv2 = 0 -0.1 0.1 a i oe oe input current oe = 1 -0.1 0.1 a oe = 0 -0.1 0.1 a i oecon oecon input current oe = 1 -1 1 a oe = 0 -1 1 a i vdd vdd quiescent current (v avdd < 4v) cpv1 = cpv2 = 0, stv = 0, oe = 0 250 500 a iv on_quiescent v on quiescent current (v avdd < 4v) cpv1 = cpv2 = 0, stv = 0, oe = 0 700 1100 a iv off_quiescent v on quiescent current (v avdd < 4v) cpv1 = cpv2 = 0, stv = 0, oe = 0 600 1000 a uvlo uvlo on von activation threshold 13 v de-activation threshold 10 v v il level shift low input voltage cpv1, cpv2, stv, oe 0.4 v v ih level shift high input voltage cpv1, cpv2, stv, oe 70% v dd v v threshold oecon threshold voltage stv = 0, oe = 3.3v 1.6 1.7 v v ol level shift low output voltage ckv1, ckv2, ckvb1, ckvb2, stvp no load -13.5 v v oh level shift high output voltage ckv1, ckv2, ckvb1, ckvb2, stvp no load 19.5 v t r _ckv ckv rise time ckv rise time from +6v to +17v 0.73 s t f _ckv ckv fall time ckv fall time from 0v to -11v 0.73 s t r _stvp stvp rise time stvp rise time from -7v to +13v, c load = 4.7nf and in series with r load = 200 0.5 s t f _stvp stvp fall time stvp fall time from +13v to -7v, c load = 4.7nf and in series with r load =200 0.28 s t d -oe-ckv+ ckv rising edge delay time oe risi ng above 1.65v to ckv crossing + 11.5v 0.68 s t d -oe-ckv- ckv falling edge delay time oe ri sing above 1.65v to ckv crossing - 5.5v 0.68 s t d -stvp+ stvp rising edge delay time stv cros sing 1.65v to stvp crossing + 3v, 0.48 s t d -stvp- stvp falling edge delay time oe ri sing above 1.65v to ckv crossing - 5.5v 0.35 s t d -ckv-cs+ ckv_cs rising edge delay time cpv falling below 1.65v to ckv crossing - 11v 1.6 2.44 s t d -ckv-cs- ckv_cs falling edge delay time cpv falling below 1.65v to ckv crossing + 17v 1.6 2.44 s i 2 c dc specification a vdd = 10v, v out = 5v, r set = 24.9k a vdd a vdd supply range vdd range 2.6v to 3.6v 4.5 18 v vdd range 2.25v to 3.6v 4.5 13 v -i dd_dcp v dd supply current (note 5) 50 a electrical specifications vdd = v in = 3.3v, a vdd = 12v, v on = 20v, v off = -14v, t a from -40c to +85c, fcpv1 and fcpv2 = 105khz, unless otherwise specified. unless ot herwise specified, parts are 100% tested at +25c. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit isl97648
6 fn6684.0 april 14, 2008 i avdd_dcp avdd supply current (note 3) 25 a set vr set voltage resolution 7bits set dn set differential non-linearity monotonic over-temperature 1 lsb set zse set zero-scale error 2 lsb set fse set full-scale error 8 lsb iset set current through r set (note 6) 20 a set er set external resistance to gnd, a vdd = 18v 10 200 k to gnd, a vdd = 4.5v 2.25 45 k a vdd to set a vdd to set voltage attenuation (note 4) 1:20 v/v out st out settling time to 0.5 lsb error band (note 4) 8 s v out out voltage range vset + 0.5v avdd v set vd set voltage drift (note 4) <10 mv vih s sda, scl, scl_s, wpn input logic high 0.7* vdd v vil s sda, scl, scl_s, wpn input logic low 0.3* vdd v sda, scl, scl_s, wpn hysteresis (note 4) 0.22*vdd v il wpn wpn il 30 37 a voh s sda, scl output logic high @ 3ma 0.4 v vol s sda, scl output logic low @ 3ma 0.4 v voh wpp wpp output logic high @ 3ma vdd - 0.4 v vol wpp wpp output logic low @ 3ma 0.4 v t dwpp wpp delay 100 ns r scl scl_s to scl on-resistance 75 t s delay from scl_s to scl 60 ns i 2 c f scl scl clock frequency 0 400 khz t sch i 2 c clock high time 0.6 s t scl i 2 c clock low time 1.3 s t dsp i 2 c spike rejection filter pulse width 0 50 ns t sds i 2 c data set-up time 100 ns t sdh i 2 c data hold time 0900ns t icr i 2 c sda, scl input rise time dependent on load (note 4) 20 + 0.1*cb 1000 ns t icf i 2 c sda, scl input fall time (note 4) 20 + 0.1*cb 300 ns t buf i 2 c bus free time between stop and start 1.3 s t sts i 2 c repeated start condition set-up 0.6 s t sth i 2 c repeated start condition hold 0.6 s t sps i 2 c stop condition set-up 0.6 s cb i 2 c bus capacitive load (note 4) 400 pf c sda capacitance on sda (note 4) 10 pf electrical specifications vdd = v in = 3.3v, a vdd = 12v, v on = 20v, v off = -14v, t a from -40c to +85c, fcpv1 and fcpv2 = 105khz, unless otherwise specified. unless ot herwise specified, parts are 100% tested at +25c. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit isl97648
7 fn6684.0 april 14, 2008 c s capacitance on scl, scl_s wpn = 0 (note 4) 10 pf wpn = 1 (note 4) 22 pf t w write cycle time 100 ms notes: 3. tested at a vdd = 18v. 4. limits established by characterization and are not production tested. 5. simulated maximum current draw when programming eeprom is 23ma, should be considered when designing power supply. 6. a typical current of 20a is calculated using the a vdd = 10v and r set = 24.9k . the maximum suggested set current should be 120a. electrical specifications vdd = v in = 3.3v, a vdd = 12v, v on = 20v, v off = -14v, t a from -40c to +85c, fcpv1 and fcpv2 = 105khz, unless otherwise specified. unless ot herwise specified, parts are 100% tested at +25c. temperature limits established by characterization and are not production tested. (continued) parameter description conditions min typ max unit timing diagrams oe cpv ckv t d_ oe_ckv+ t r_ ckv t d_ ckv_cs+ -11v 17v 11.5v 6v 17v t d_ ckv_cs- t d_ oe_ckv- 0v -5.5v -11v t r_ ckv 1.65v 0v 1.65v 0v 3.3v 3.3v figure 1. timing diagram of oe, cpv, and ckv stv stvp t d_ stvp+ t d_ stvp- 13v 3v -7v t r_ stvp t r_ stvp 13v 3v -7v 3.3v 1.65v 0v figure 2. timing diagram of stv and stvp isl97648
8 fn6684.0 april 14, 2008 typical application diagram 10 2k h f f f f f f f f 100nf 4.7f isl97648
9 fn6684.0 april 14, 2008 pin descriptions pin number pin name description 1 ckvcs1 discharge switch inpu t 1, ckv1 charge share 2 ckvbcs1 discharge switch input 1, ckvb1 charge share 3 ckvb1 high voltage output 1 , scan clock even 4 stvp1 high voltage output 1, scan start pulse 1 5 stvp2 high voltage output 2, scan start pulse 2 6 ckvb2 high voltage output 2, scan clock even 7 ckvbcs2 discharge switch input 2, ckvb2 charge share 8 ckvcs2 discharge switch inpu t 2, ckv2 charge share 9 ckv2 high voltage output 2, scan clock odd 10 stv1 v sync timing, v sync1 11 stv2 v sync timing, v sync2 12 cpv1 h sync timing, h sync clock 1 13 cpv2 h sync timing, h sync clock 2 14 oe h sync timing, h sync clock 3 15 oecon oe disable input, oe blank 16 lgnd logic gnd 17 dish discharge function input, v off discharge 18 vdd logic power supply for scan driver and module calibrator 19 wpn write protection active low. cmos level. 20 scl_s serial clock input. 21 scl serial clock input for internal and inter-ic use. 22 sda i 2 c serial data input/output. 23 wpp write protection active high. cmos level. 24 rset maximum sink current adjustment point. connec t a resistor from set to gnd to set the maximum adjustable sink current of the out pin. the maxi mum adjustable sink current is equal to (avdd/20) divided by rset. 25 out adjustable sink current output pi n. the current sinks into the out pin is equal to the dac setting times the maximum adjustable sink current divided by 12 8. see set pin function de scription for the maxim adjustable sink current setting. 26 in1+ op amp 1 non-inverting input 27 in1- op amp 1 inverting input 28 vcom1 op amp 1 output 29 in2+ op amp 2 non-inverting input 30 in2- op amp 2 inverting input 31 vcom2 op amp 2 output 32 in3+ op amp 3 non-inverting input 33 in3- op amp 3 inverting input 34 vcom3 op amp 3 output 35 in4+ op amp 4 non-inverting input 36 in4- op amp 4 inverting input 37 vcom4 op amp 4 output isl97648
10 fn6684.0 april 14, 2008 38 cgnd vcom gnd 39 avdd vcom amplifier positive supply pin 40 test test pin 41 sw1 boost switch output 1 42 sw2 boost switch output 2 43 pgnd1 boost ground pins 44 pgnd2 boost ground pins 45 vin boost supply voltage 46 en chip enable 47 agnd analog gnd 48 comp boost compensation pin 49 fb a vdd boost feedback pin 50 rhvs voltage set pin for hvs test 51 hvs high-voltage stress input select pin 52 temp temperature sensor output voltage 53 voff negative supply 54 sgnd scan driver gnd 55 von positive supply 56 ckv1 high voltage output 1 , scan clock odd pin descriptions (continued) pin number pin name description typical performance curves figure 3. boost efficiency @ vin = 5v figure 4. boost efficiency @ vin = 3.3v 60 65 70 75 80 85 90 95 efficiency (%) 0 200 400 600 800 1000 i out (ma) 5.0v v in to 15.7v v out 5.0v v in to 10.7v v out 0 100 200 300 400 500 i out (ma) efficiency (%) 3.3v v in to 10.7v v out 3.3v v in to 15.7v v out 60 65 70 75 80 85 90 95 isl97648
11 fn6684.0 april 14, 2008 figure 5. boost load regulation @ avdd = 10.7v figure 6. boost load regulation @ avdd = 15.7v figure 7. boost line regulation @ i out = 50ma figure 8. boost transient response figure 9. vcom slew rate figure 10. temperature sensor output vs junction temperature typical performance curves (continued) -0.05 0 0.05 0.10 0.15 0.20 0 300 600 900 1200 i out (ma) v in = 5.0v boost load regulation (%) v in = 3.3v -0.05 0 0.05 0.10 0.15 0.20 0 200 400 600 800 i out (ma) boost load regulation (%) v in = 5.0v v in = 3.3v 0 0.1 0.2 0.3 0.4 0.5 0.6 245 v in (v) boost line regulation (%) 3 a vdd = 15.7v a vdd = 10.7v ch4 = i out ch3 = a vdd (ac coupled) input signal output signal 0 500 1000 1500 2000 2500 -50 -25 0 25 50 75 100 125 150 175 temperature(c) v temp (mv) isl97648
12 fn6684.0 april 14, 2008 figure 11. vdd supply current vs vdd figure 12. v on suply current vs v on figure 13. v off supply current vs v off figure 14. level shift power consumption vs cpv frequency figure 15. level shift power consumption vs cpv frequency figure 16. v out vs setting typical performance curves (continued) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.0 1.0 2.0 3.0 4.0 5.0 vdd (v) i vdd (ma) v on = 20v v off = 14v 0 100 200 300 400 500 600 700 800 900 0 1020304050 v on (v) i von (a) all inputs low vdd = 3.3v v off = -14v 0 200 400 600 800 -30-25-20-15-10 -5 0 v off (v) i voff (a) all inputs low vdd = 3.3v v on = 20v 0 200 400 600 800 1000 1200 1400 0 40k 80k 120k 160k input frequency (hz) 4700pf 2200pf v on = 20v v off = -14v r cs = 500 power dissipation (mw) 0 500 1000 1500 2000 2500 3000 3500 0 40k 80k 120k 160k input frequency (hz) 4700pf 2200pf v on = 35v v off = 20v r cs = 500 power dissipation (mw) 4.00 4.20 4.40 4.60 4.80 5.00 5.20 5.40 0 20406080100120 setting v out (v) r 1 = 100k r 2 = 90.9k r set = 24.3k a vdd = 10v isl97648
13 fn6684.0 april 14, 2008 application information a vdd boost converter the a vdd boost converter features a fully integrated 2.7a boost fet. the regulator uses a current mode, pi control scheme which provides good line regulation and good transient response. a network connected to the comp pin is used to compensate the device. in normal operation the output voltage is set using a re sistor divider to the feedback pin fbb. the feedback reference voltage is set is to 1.23v. in continuous current mode, curr ent flows continuously in the inductor during the entire switching cycle in steady state operation. the voltage conversion ratio in continuous current mode is given by equation 1: where d is the duty cycle of the switching mosfet. the boost converter uses a summ ing amplifier architecture consisting of gm stages for voltage feedback, current feedback and slope compensatio n. a comparator looks at the peak inductor current cycle by cycle and terminates the pwm cycle if the current limit is reached. an external resistor divider is required to divide the output voltage down to the nominal reference voltage. current drawn by the resistor network should be limited to maintain the overall converter efficiency. the maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. a resistor network in the order of 60k is recommended. the boost converter output voltage is determined by equation 2: the current through the mosfet is limited to 2.7a peak . this restricts the maximum out put current (average) based on equation 3: where il is peak-to-peak inductor ripple current, and is set by equation 4: where f s is the switching frequency. the minimum boost duty cycle of the isl97648 is ~20% for 1.4mhz. when the operating duty cycle is lower than the minimum duty cycle, the part will not switch in some cycles randomly, which will cause some lx pulses to be skipped. in this case, lx pulses are not consistent any more, but the output voltage (a vdd ) is still regulated by the ratio of r 1 and r 2 . because some lx pulses are skipped, the ripple current in the inductor will become bigger. under the worst case, the ripple current will be from 0 to the threshold of the current limit. in turn, the bigger ripple current will increase the output voltage ripple. hence, it will need more output capacitors to keep the output ripple at the same level. when the input voltage equals, or is larger than, the output voltage, the boost converter will stop switching. the boost converter is not regulated any more, but the part will still be on and other channels are still regulated. boost converter input capacitor an input capacitor is used to suppress the voltage ripple injected into the boost converter. a ceramic capacitor with capacitance larger than 10f is recommended. the voltage rating of input capacitor shoul d be larger than the maximum input voltage. some capacitors are recommended in table 1 for input capacitor. boost inductor the boost inductor is a critic al part which influences the output voltage ripple, transient response, and efficiency. values of 3.3h to 10h should be selected to match the internal slope compensation. the inductor must be able to handle the following average and peak current shown in equations 5 and 6: some inductors are recommended in table 2. rectifier diode (b oost converter) a high-speed diode is necessary due to the high switching frequency. schottky diodes are recommended because of their fast recovery time and low forward voltage. the reverse voltage rating of this diode should be higher than the maximum output voltage. the rectifier diode must meet the output current and peak inductor current requirements. v boost v in ----------------------- - 1 1d ? ------------- = (eq. 1) v boost r 1 r 2 + r 2 -------------------- - v fb = (eq. 2) i omax i lmt i l 2 -------- ? ?? ?? v in v o --------- = (eq. 3) i l v in l --------- d f s ---- - = (eq. 4) table 1. boost converter input capacitor recommendation capacitor size vendor part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k table 2. boost inductor recommendation inductor dimensions (mm) vendor part number 6.8h/ 3a peak 7.3x6.8x3.2 tdk rlf7030t-6r8n3r0 6.8h/ 2.9a peak 7.6x7.6x3.0 sumida cdr7d28mnnp-6r8nc 5.2h/ 4.55a peak 10x10.1x3.8 cooper bussmann cd1-5r2 i lavg i o 1d ? ------------- = (eq. 5) i lpk i lavg i l 2 -------- + = (eq. 6) isl97648
14 fn6684.0 april 14, 2008 table 3 shows some recommendations for boost converter diode. output capacitor the output capacitor supplies the load directly and reduces the ripple voltage at the output. output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the esr of output capacitor, and the charging and discharging of the ou tput capacitor, as shown in equation 7. for low esr ceramic capacitors, the output ripple is dominated by the charging and discharging of the output capacitor. the voltage rating of the output capacitor should be greater than the maximum output voltage. note: capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across then increases. c out in equation 7 assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at 0v. table 4 shows some selections of output capacitors. loop compensation (boost converter) the boost converter of isl97648 can be compensated by a rc network connected from vc pin to ground. c c = 4.7nf and r c = 10k rc network is us ed in the demo board. a higher resistor value can be used to lower the transient load change a vdd overshoot (however, this may be at the expense of stability to the loop). the stability can be examined by repeatedly changing the load between 100ma and a max level that is likely to be used in the system being used. the a vdd voltage should be examined with an oscilloscope set to ac 100mv/div and the amount of ringing observed when the load current changes. reduce excessive ringing by reducing the value of the resistor in series with the comp pin capacitor. hvs operation when the hvs input is taken high, the isl97648 enters hvs test mode. in this mode, the output of a vdd is increased by switching rset-hvs to ground to select the test voltage. fault protection the isl97648 integrates ovp, ocp and over-temperature protection. temperature sensor the isl97648 also includes a te mperature output for use in system thermal management contro l. the integrated sensor measures the die temperatur e over the 0c to +150c range. output is in the form of an analog voltage on the temp pin in the range of 0.5v to 2.0v. temperature accuracy is 5c. soft-start the isl97648 integrates the so ft-start function and the timing diagram is shown in the figure 17. the boost switch goes through soft-start sequence after the en pin is pulled to high. high performance vcom amplifiers the vcom amplifiers are desig ned to control the voltage on the back plate of an lcd display or to drive the repaired column lines. the plate is capacitive coupled to the pixel drive voltage which alternatel y cycles positive and negative at the line rate for the display. thus, the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few 100ma for typical applications). the isl97648 vcom amplifier?s output current is limited to 150ma. this limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. it does not necessarily prevent a large temperature rise if the current is maintained (in this case the whole chip may be shut down by the thermal trip to protect functionality.) if the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir table 3. boost converter rectifier diode recommendation diode v r /i avg rating package vendor ss23 30v/2a smb fairchild semiconductor sl23 30v/2a smb vishay semiconductor table 4. boost output capacitor recommendation capacitor size vendor part number 10f/25v 1210 tdk c3225x7r1e106m 10f/25v 1210 murata grm32dr61e106k v ripple i lpk esr v o v in ? v o ----------------------- - i o c avdd ------------------- - 1 f s --- - + = (eq. 7) figure 17. boost soft-start of current limit en i ocp i switch i ocp /8 t ss isl97648
15 fn6684.0 april 14, 2008 capacitor back up once the pulse has stopped. this will happen on the s time scale in practical systems and for pulses 2x or 3x the current limit, the v com voltage will have settled again before the next line is processed. level shifter general description the isl97648 is a high performance 65v tft-lcd level shifter. it level shifts ttl le vel timing signals from the video source into 65v peak-to-peak output voltage. its output is capable of delivering 100ma peak current into 5nf of capacitive load. it also incorporates logic to control the output timings. the logic timing control circuit is powered rom vdd supply. figure 18 shows the system block diagram related to level shifter part. input signals the device performs beside of level transformation also logic operation between the input signals: ? stv1 - vertical sync timing signal 1, frequency range from 60hz to 120hz ? stv2 - vertical sync timing signal 2, frequency range from 60hz to 120hz ? cpv1- horizontal sync timing signal 1, frequency range up to 166khz ? cpv2- horizontal sync timing signal 2, frequency range up to 166khz ? oe- output enable write signal, frequency range up to 332khz output signals the output signals, ckv and ckvb are generated by isl97648 internal switches. figure 19 depicts the simplified schematic of the output stage and interface. c l capacitors model the capacitive loading appeared at the inputs of the tft-lcd panel for the ckv1, ckvb1, ckv2, and the ckvb2 signals. the c l is typically between 1nf and 5nf. in addition to switches sw1, sw2, sw3, sw4, sw5, sw6, sw7, and sw8, the ninth and tenth switches are added to reduce the power dissipation and shape the output waveform. figure 19 shows the location of the additional sw9 and sw10 switches. video source stv2 cpv1 cpv2 oe isl97648 stvp1 ckv1 ckvcs1 ckvbcs1 ckvb1 ckv2 ckvcs2 ckvbcs2 ckvb2 high voltage a-si shift register column driver high voltage a-si shift register avdd vcom stvp2 stv1 figure 18. system block diagram related to level shift output isl97648
16 fn6684.0 april 14, 2008 . in reality, each switch consists of two such switches, one for the positive discharge and one for the negative discharge, see figure 20.. due to the actual solid-state co nstruction of the switches, the capacitors c l does not get discharged entirely. the amount of left over charges depends on the value of the voltages of v on and v off on the capacitors. internal logic block diagram figure 21 shows the internal block diagram. in order to reduce power dissipation, most of the logic circuitry is powered from vdd logic supply. the output of the vdd logic is level-shifted to drive the output switches. internal logic table ckv, ckb, ckvcs and ckvbcs the internal logic block of ckv1 and ckv2 are identical and only one logic block and truth table are shown in figure 21 and table 5. to generate the ckv, ckvb and charge sharing outputs, the internal logic goes through 3 steps as outlined in the following paragraphs. step 1: generation of internal clock from the inputs, step 2: the clk clock dries a flip-flop with complementary output q and q . the flip-flop is reset by stv signal. step 3: the 2 complementar y outputs ckv and ckvb can be high, low or high-impedance, as shown in table 7: hi-z is output high impedance and charge sharing is enabled. na is illegal state and cannot occur. stvp stvp output is controlled by stv input and the internal clk signal. table 8 shows the relationship: figure 19. simplified schematic of output stage figure 20. bi-directional switches ckvcs1 ckvcs2 ckvbcs2 ckvbcs1 sw9 sw10 sw9 sw10 table 5. clk signal generation cpv oe oecon clk 0000 0010 0101 0110 1001 1011 1101 1111 table 6. internal flip-flop outputs clk stv q q 0 --> 1 0 q (n-1) q(n-1) x101 table 7. ckv, ckvb, ckvcs and ckvbcs clk q stv ckv ckvb 000hi-zhi-z 010hi-zhi-z 1 0 0 low high 1 1 0 high low 001nana 0 1 1 low high 101nana 1 1 1 high low table 8. stvp output clk stv stvp 0 0 low 01high 1 0 low 11hi-z clk cpv oe oecon ? () = oecon low( stv = high) = oecon hi z( stv = low) ? = isl97648
17 fn6684.0 april 14, 2008 figure 21. internal logic block diagram isl97648
18 fn6684.0 april 14, 2008 output waveforms figure 22 shows a typical ckv and ckvb output waveforms. the output droop rate depends on the external discharge resistor value and the output capacitor load. figure 23 shows the delay time between the incoming horizontal sync timing pulse cpv and the generated output pulses. t is dependent mainly on the value of c l . figure 24 shows the effect of stv.. auxiliary functions dish: it discharges v off when the logic power voltage level drops out, when 'dish' is < -0.6v (v cc system power turns off), v off is connected to ground level by 1k . oecon: it provides continuos polarity changes to the tft-lcd panel during the vertical blanking. power dissipation the dissipated power of chagrge sharing in r 1 and r 2 could be calculated as follows: we assume that: ?v on = 40v ?v off = -20v ?h sync timing (cpv); frequency = 60khz ?c l = 5nf the value of v l , the left over voltage in the capacitors in that case is 23v for the positive discharge and 3.0v for the negative discharge. the voltage change across t he capacitor is therefore 23v (see figure 25). the stored energy in the capacitor is shown in equation 8: the energy which is stored in the capacitor will be dissipated on the resistor (see figure 26). the switch will close 60,000 in every second. since the process will be repeated 2x, for the ckv and the ckvb. in 60,000 cycles per seco nd the power dissipation in r 1 and r 2 becomes equation 9. the dissipated power of level shift driving in r la and r lb could be calculated as follows: the voltage change across the capacitor is 37v when the level shift driving the capacitor to v on or v off (see figure 27). the stored energy in the capacitor is calculated in equation 10: consequently, in 60,000 cycles per second the power dissipation in r la and r lb becomes equation 11: since there are also the same power consumption at r 3 , r 4 , r lc and r ld , the total power dissipation is equation 12: figures 25, 26, 27, and 28 show the total power dissipation over a range of possible voltages, operating frequencies and loads. the values of the r 1 and r 2 must be selected such that the capacitor c l is discharged via r 1 or r 2 resistor in one half period of the h sync timing. care should be taken to prevent the power from exceeding the maximum rating of the package. figure 23. cpv to ckv/ckvb delay ckv ckvb figure 22. ckv and ckvb output waveforms ckv ckvb cpv ckv ckvb stv cpv figure 24. effect of stv 1/2 v 2 c1/223 2 5 10 -9 1.32 w = = (eq. 8) 21.3210 -6 60 x10 3 160mw = (eq. 9) 1/2 v 2 c1/237 2 5 10 -9 3.42 w = = (eq. 10) 23.4210 -6 60 x10 3 410mw = (eq. 11) 2x 410 160 + () 1140mw = (eq. 12) isl97648
19 fn6684.0 april 14, 2008 isl97648 i 2 c lcd module calibrator truth table figure 25. voltage change across the capacitor when charge sharing between ckv and ckvb figure 26. energy dissipated on the resistor when charge sharing figure 27. voltage change across the capacitor when driving figure 28. energy dissipated on the resistor when driving +40v +17v 3.0v -20v 23v 23v 23v c r 12 sw +40v +17v 3.0v -20v 37v 37v 37v c r 12 sw table 9. dvr write protection truth table input output wpn scl_s scl wpp register eeprom low unused input high write protect write protect high connected to scl connected to scl_s low writeable writeable high to low disconects from scl disconects from scl_s low to high eeprom is read into register eeprom is read into register float (pull-down resistor included) unused input high write protect write protect note: when the device is not write-protected scl_s and scl signals should not be driven at the same time. when scl_s signal is ? unused? should be left floating.
20 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6684.0 april 14, 2008 i 2 c bus format output connection this device provides the ability to reduce the flicker of an lcd panel by adjustment of the vcom voltage during production test and alignment. a 128-step resolution is provided under digital control, which adjusts the sink current of the output. the output is co nnected to an external voltage divider, so that the device will have the capability to reduce the voltage on the output by increasing the output sink current (see figure 29). the adjustment of the output is provided by the 2-wire i 2 c serial interface. adjustable sink current output the device provides an output sink current which lowers the voltage on the external voltage divider. equations 13 and 14 control the output. see figure 29. note: where setting is an integer between 1 and 128. ramp-up of the vdd power supply it is required that the ramp-up from 10% vdd to 90% vdd level be achieved in less than or equal to 10ms to assure that the eeprom and power-on-reset circuits are synchronized and the correct value is read from the eeprom memory. start slave address w astop 10 0 1111 d6 d5 d4 d3 d2 d1 d0 p scl sda start r rw a d6 d5 d4 d3 d2 d1 d0 p 0 0 stop when read operation, don?t care p. p = 1: register writing p = 0: eeprom writing (program) p: program adata r set figure 29. output connection circuit example - + isl97648 set out avdd r 1 r 2 avdd iout setting 128 -------------------- - x avdd 20 rset () ---------------------------- - = (eq. 13) vout r2 r1 r2 + ---------------------- ?? ?? vavdd 1 setting 128 -------------------- - x r1 20 rset () ---------------------------- - ? ?? ?? = (eq. 14) isl97648
21 fn6684.0 april 14, 2008 isl97648 package outline drawing l56.8x8d 56 lead thin quad flat no-lead plastic package rev 0, 04/07 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 42 29 14 1 15 28 43 56 b (4x) 0.15 index area pin 1 a 8.00 b 8.00 52x 0.50 6.5 4x pin #1 index area 56x 0 . 4 0 . 1 b 0.10 ma c 4 6 . 50 0 . 15 0 . 75 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5 ( 7 . 8 typ ) ( 6 . 5 ) ( 52x 0 . 5 ) ( 56x 0 . 25 ) ( 56x 0 . 6 ) 6 6 0.25 +0.05 / -0.07 package outline

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